1. Field of the Invention
This invention relates to the field of signal processing, and in particular to a Sigma-Delta Fractional-N divider that provides resolution with a step size of a half clock cycle.
2. Description of Related Art
In a Sigma Delta fractional-N frequency synthesizer, a fractional dividing ratio is achieved by averaging a time series, termed a sigma-delta sequence, which is generated by sigma-delta modulation. If the desired ratio is between the integers N and N+1, the input signal is divided by N at some periods, and divided by N+1 for other periods. The relative number of times the clock is divided by N, compared to the number of times that it is divided by N+1, determines the average frequency of the output signal. If, for example, the input signal is alternately divided by N, then N+1, then N, and so on, the average divider output frequency will be the frequency of the input signal divided by (N+0.5). If the input signal is divided more often by N than by N+1, the divisor will be less than (N+0.5); if it is divided more often by (N+1), the divisor will be greater than (N+0.5).
Higher order sigma-delta fractional-N frequency synthesizers are known in the art, wherein the choice among integer divisions is not limited to the choice between N and (N+1). In a higher order sigma-delta fractional-N frequency synthesizer, the integer division may be selected from among a set of integers N+s, where s is an integer, for example, with the range of xe2x88x921 to +2 for a second order (22 selections) sigma-delta device, and xe2x88x923 to +4 for a third order (23 selections) device, and so on. An example second-order sigma-delta calculator is illustrated in FIG. 3. A first order (21 selections) sigma-delta fractional-N frequency synthesizer is presented herein as a paradigm for ease of understanding of this invention.
FIG. 1 illustrates an example block diagram of a conventional fractional-N frequency synthesizer 100 that is configured in a phase-locked loop configuration. A phase comparator 110 detects a difference between a reference input signal and a feedback signal from a fractional-N divider 140. This difference is filtered by a loop filter 120, and the filtered difference controls the output frequency of a voltage-controlled oscillator 130. The output signal of the oscillator 130 is fed back to the fractional-N divider 140, to be divided by either N or N+1, as discussed above, via the integer divider 150. The control of whether the integer divider 150 divides by N or by N+1 is provided by a sigma-delta calculator 160, discussed further below. The phase-locked loop of the synthesizer 100 is designed to minimize the phase difference between the input reference signal, and the frequency-divided output signal of the fractional-N divider 140. If the dividing ratio is exactly N, the output frequency from the voltage controlled oscillator 130 will be N times the input reference frequency. If the dividing ratio is alternately N for three periods, then N+1 for one period, then N for three periods, etc., the output frequency will be (N+0.25) times the input reference frequency, the (N+0.25) term being the average of the four repeating periods (3*N+1*(N+1))/4.
The sigma-delta calculator 160 controls whether the integer divider 150 effects a divide-by-N operation, or a divide-by-(N+1) operation. At each cycle of the frequency-divided output, a constant value K, corresponding to a fractional dividing ratio, is added to an intermediate sum, and an output pulse is produced whenever a carry term is produced from this addition. This output pulse effects the division by (N+1); if the output pulse is not asserted, the divider 150 divides by N. If the fractional component is small, such as 0.1, a carry is rarely generated; in this example, only once per ten cycles, and thus the divider 150 will provide nine divisions by N for each one division by (N+1), thereby producing an average division by (N+0.1). Whereas, if the fractional component is large, such as 0.9, a carry is generated frequently; in this example every nine out of ten clock cycles will effect a division by (N+1) and only one division by N, thereby producing an average division by (N+0.9).
In this process of providing a fractional division via a series of integer division with different divisors, a systematic phase shift is introduced by the series of integer divisions that are used to effect the fractional division. In the example of nine divisions by N, followed by a division by (N+1), at each division by N, the frequency-divided output signal will increasingly lead the reference signal; then, at the divide-by-(N+1) period, the output signal will be delayed by an xe2x80x9cextraxe2x80x9d clock cycle, allowing the reference signal to xe2x80x9ccatch upxe2x80x9d. Optionally, the sigma-delta calculator 160 may be configured to compensate, via the loop filter 120, for this systematic phase shift, as indicated by the dotted line between the two. The aforementioned intermediate sum provides an indication of the amount of lead or lag of the frequency-divided output signal, and is provided to the loop filter 120, or to the phase detector 110, to compensate for this fractional-division, using techniques common in the art.
The correction of the systematic phase shift, as well as the accurate generation of a feedback signal that corresponds to the differences between the reference signal input and the output of the frequency divider, is highly dependent upon the linearity of the components used to provide the mapping between phase-difference and the correction voltage that corresponds to the correction of this phase-difference. When a circuit is non-linear, the non-linear effect will typically be more evident for an input signal with a large span of values, than for an input signal with a relatively small span of values, because the non-linear effect may be substantially xe2x80x98piece-wisexe2x80x99 linear over a small span. Thus, a phase difference that spans a wide range can introduce multiplicatively worse affects when processed via conventional devices that exhibit some non-linearity.
As is known in the art, for the same output frequency, a higher reference clock frequency will result in a better noise and spur performance, as well as a faster response time. In the frequency domain, the aforementioned periodic xe2x80x9ccatch-upxe2x80x9d corresponds to a xe2x80x98spurxe2x80x99 on each side of intended output frequency, the distance of the spur from the output frequency being determined by the frequency of the periodic catch-ups. A higher reference clock frequency results in a higher frequency-divided output signal. The higher frequency-divided output signal provides for more frequent increments of the aforementioned intermediate counter, thereby effectively allowing for smaller cumulative phase shifts. For example, if the reference clock is doubled, the aforementioned 9-out-of-10 ratio of divide-by-N periods to total periods becomes an 18-out-of-20 ratio. During this 18-out-of-20 sequence, however, the first divide-by-(N+1) period will occur after nine divide-by-N periods. That is, the sigma-delta calculator 160 will provide twice as many assertions of the divide-by-(N+1) command during the same overall time period, and thus the frequency of xe2x80x9ccatching upxe2x80x9d to the accumulating systematic phase error is doubled. Effectively, the accumulating systematic phase error is reduced in half. Depending upon the configuration of the phase locked loop 100, this halving of the systematic phase error can provide a multiplicative reduction in noise and spur performance. In addition to reducing the magnitude of the systematic phase error, thereby making the synthesizer less sensitive to the aforementioned non-linear effects of conventional components, a higher catch-up frequency provides a larger separation between the spurs and the desired output frequency component, thereby easing the task of filtering the spurs from the desired output frequency component. Providing a higher frequency reference clock also increases the achievable resolution in the fractional divider. In the aforementioned increase from 10 to 20 reference cycles per cycle, for example, the inherent resolution improves from 0.1 ({fraction (1/10)}) to 0.05 ({fraction (1/20)}).
Providing a higher reference frequency reference clock, however, is often not feasible. In some applications, the EMI (ElectroMagnetic Interference) or RF (Radio Frequency) separation constraints preclude a higher frequency. In other applications, the higher power consumption of a higher frequency clocking system provides a practical upper-limit to the frequencies that can be employed.
It is an object of this invention to provide a sigma-delta fractional-N frequency synthesizer having improved noise and spur performance. It is a further object of this invention to provide a sigma-delta fractional-N frequency synthesizer having improved noise and spur performance without a corresponding increase in the frequency of the reference clock signal. It is a further object of this invention to provide a sigma-delta fractional-N frequency synthesizer having improved noise and spur performance and reduced power consumption. It is a further object of this invention to provide a sigma-delta fractional-N frequency sythesizer having improved resolution.
These objects and others are achieved by providing a frequency synthesizer that allows for a direct fractional division of the synthesized frequency. Specifically, the frequency synthesizer allows for a half-cycle division of the synthesized frequency. In a conventional sigma-delta fractional-N frequency synthesizer, a controllable divider is configured to allow for the division of the synthesized frequency by an integer factor of N or an integer factor of N+1. A sigma-delta calculator of this invention controls a half-cycle divider so as to selectively divide the synthesized frequency by an integer factor of N, or a fractional factor of (N+xc2xd). If a higher order sigma-delta calculator is employed that provides S output symbols, the half-cycle divider is correspondingly controlled to select a division factor of (N+s/2), where s is selectable from set of S symbols.